UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 456

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.4 Operation
10.4.1 Watch timer operations
(INTWT) at fixed, exact time intervals of 0.25 or 0.5 seconds.
11-bit prescaler and 5-bit counter are cleared and counting stops.
the watch timer is operating at the same time as the interval timer. At this time, an error of up to 15.6 ms may occur in
the watch timer, but the interval timer is not affected.
BGCS00 bits and the 8-bit comparison value using the PRSCM0 register, and set the count clock frequency (f
the watch timer to 32.768 kHz.
PRSCM0 register.
454
The watch timer operates on the main clock or subclock (32.768 kHz) and generates an interrupt request signal
Counting starts when the WTM.WTM1 and WTM.WTM0 bits are set to 11. When the WTM0 bit is cleared to 0, the
The time of the watch timer can be adjusted by clearing the WTM1 bit to 0 and then clearing the 5-bit counter when
If the main clock is used as the count clock of the watch timer, set the count clock using the PRSM0.BGCS01 and
When the PRSM0.BGCE0 bit is set to 1, f
f
To set f
<1> Set N = f
<2> When the value resulting from rounding up the first decimal place of N is even, set N before the roundup as
<3> Repeat <2> until N is odd or m = 3.
<4> Set the value resulting from rounding up the first decimal place of N to the PRSCM0 register and m to the
Example: When f
Remark m: Division value (set value of BGCS01 and BGCS00 bits) = 0 to 3
BRG
f
BRG
can be calculated by using the following expression.
N/2 and m as m + 1.
BGCS01 and BGCS00 bits.
= f
BRG
X
N: Set value of PRSCM0 register = 1 to 256
f
/(2
<1> N = 4,000,000/65,536 = 61.03…, m = 0
<2>, <3> Because N (round up the first decimal place) is odd, N = 61, m = 0.
<4> Set value of PRSCM0 register: 3DH (61), set value of BGCS01 and BGCS00 bits: 00
At this time, the actual f
f
X
BRG
: Main clock oscillator frequency
to 32.768 kHz, perform the following calculation and set the BGCS01 and BGCS00 bits and the
X
However, N = 256 when PRSCM0 register is set to 00H.
m+1
/65,536. Set m = 0.
= f
= 32.787 kHz
× N)
X
X
/(2
= 4.00 MHz
m+1
× N) = 4,000,000/(2 × 61)
BRG
frequency is as follows.
CHAPTER 10 WATCH TIMER
BRG
User’s Manual U18953EJ5V0UD
is supplied to the watch timer.
BRG
) of