UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 853

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UPD70F3738GF-GAS-AX

Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3738GF-GAS-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
<R>
Item
LVI
Subclock oscillator
Internal oscillator
PLL
CPU
DMA
Interrupt controller
Timer P (TMP0 to TMP5)
Timer Q (TMQ0)
Timer M (TMM0)
Watch timer(/RTC)
Watchdog timer 2
Serial interface
A/D converter
D/A converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
CPU register set
Internal RAM
Notes1.
Caution When the CPU is operating on the subclock and main clock oscillation is stopped, a register for
2.
Be sure to stop the PLL (PLLCTL.PLLON bit = 0).
μ
which a wait is specified must not be accessed. If a wait is generated, it can only be canceled by
a reset (see 3.4.8 (2)).
PD70F3792, 70F3793 only
Setting of Low-Voltage
Note2
CSIB0 to CSIB4
I
UARTA0 to UARTA5
UARTC0
2
Table 23-12. Operating Status in Low-Voltage Subclock Operation Mode
C00 to I
Subclock Operation
2
Note2
C02
Mode
Operable
Oscillates
Oscillation enabled
Stops operation
Operable
Stops operation (must stop)
Operable
Stops operation
Stops operation
Operable when f
Operable when f
Operable when f
Stops operation
(When the SCKBn input clock is selected as the count clock, be sure to stop the
SCKBn input clock (n = 0 to 4).)
Stops operation
Stops operation
(When the ASCKA0 input clock to UARTA0 is selected, be sure to stop the ASCKA0
input clock.)
Stops operation
Stops operation
Stops operation (must stop)
Stops operation (output held)
Operable
Stops operation (must stop)
See 2.2 Pin States.
Settable
Settable
CHAPTER 23 STANDBY FUNCTION
User’s Manual U18953EJ5V0UD
Note1
R
XT
R
/8 or f
/8 or f
is selected as the count clock
Main Clock Is Stopped (Must Be Stopped)
XT
XT
is selected as the count clock
is selected as the count clock
Operating Status
851

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