UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 625

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Therefore, the maximum baud rate that can be received by the destination is as follows.
Similarly, obtaining the maximum allowable data frame length yields the following.
Therefore, the minimum baud rate that can be received by the destination is as follows.
Obtaining the allowable baud rate error for UARTC0 and the destination from the above-described equations
yields the following.
Remarks 1. The reception accuracy depends on the bit count in 1 frame, the base clock
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (
4
8
20
50
100
255
Division Ratio (k)
10
11
BRmax = (FLmin/11)
BRmin = (FLmax/11)
Table 17-7. Maximum/Minimum Allowable Baud Rate Error (11-Bit Length)
× FLmax = 11 × BL −
FLmax =
2. k: Setting value of UC0CTL2.UC0BRS7 to UC0CTL2.UC0BRS0 bits (n = 0 to
frequency (f
frequency (f
2)
21k − 2
Maximum Allowable Baud Rate Error
20 k
−
−
1
1
UCLK
UCLK
=
=
BL × 11
k + 2
2 × k
21k − 2
21k + 2
) and the larger the division ratio (k), the higher the accuracy.
), and the division ratio (k). The higher the base clock
20k
22k
User’s Manual U18953EJ5V0UD
+2.32%
+3.53%
+4.26%
+4.56%
+4.66%
+4.72%
× BL =
Brate
Brate
21k − 2
2 × k
BL
Minimum Allowable Baud Rate Error
−2.43%
−3.61%
−4.31%
−4.58%
−4.67%
−4.73%
PD70F3792, 70F3793)
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