UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 331

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) 16-bit counter
(2) CCR0 buffer register
(3) CCR1 buffer register
(4) CCR2 buffer register
(5) CCR3 buffer register
(6) Edge detector
This is a 16-bit counter that counts internal clocks and external events.
This counter can be read by using the TQ0CNT register.
When the TQ0CTL0.TQ0CE bit is 0 and the counter is stopped, the counter value is FFFFH. If the TQ0CNT
register is read at this time, 0000H is read.
Reset sets the TQ0CE bit to 0, stopping the counter, and setting its value to FFFFH.
This is a 16-bit compare register that compares the value of the 16-bit counter.
When the TQ0CCR0 register is used as a compare register, the value written to the TQ0CCR0 register is
transferred to the CCR0 buffer register. If the value of the 16-bit counter matches the value of the CCR0 buffer
register, a compare match interrupt request signal (INTTQ0CC0) is generated.
The CCR0 buffer register cannot be read or written directly.
The CCR0 buffer register is cleared to 0000H after reset because the TQ0CCR0 register is cleared to 0000H.
This is a 16-bit compare register that compares the value of the 16-bit counter.
When the TQ0CCR1 register is used as a compare register, the value written to the TQ0CCR1 register is
transferred to the CCR1 buffer register. If the count value of the 16-bit counter matches the value of the CCR1
buffer register, a compare match interrupt request signal (INTTQ0CC1) is generated.
The CCR1 buffer register cannot be read or written directly.
The CCR1 buffer register is cleared to 0000H after reset because the TQ0CCR1 register is cleared to 0000H.
This is a 16-bit compare register that compares the value of the 16-bit counter.
When the TQ0CCR2 register is used as a compare register, the value written to the TQ0CCR2 register is
transferred to the CCR2 buffer register. If the count value of the 16-bit counter matches the value of the CCR2
buffer register, a compare match interrupt request signal (INTTQ0CC2) is generated.
The CCR2 buffer register cannot be read or written directly.
The CCR2 buffer register is cleared to 0000H after reset because the TQ0CCR2 register is cleared to 0000H.
This is a 16-bit compare register that compares the value of the 16-bit counter.
When the TQ0CCR3 register is used as a compare register, the value written to the TQ0CCR3 register is
transferred to the CCR3 buffer register. If the count value of the 16-bit counter matches the value of the CCR3
buffer register, a compare match interrupt request signal (INTTQ0CC3) is generated.
The CCR3 buffer register cannot be read or written directly.
The CCR3 buffer register is cleared to 0000H after reset because the TQ0CCR3 register is cleared to 0000H.
This circuit detects the valid edges input to the TIQ00 to TIQ03 pins. No edge, rising edge, falling edge, or both
the rising and falling edges can be selected as the valid edge by using the TQ0IOC1 and TQ0IOC2 registers.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
User’s Manual U18953EJ5V0UD
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