UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 498

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

496
(1) Real-time output buffer registers 0L, 0H (RTBL0, RTBH0)
Note After setting the real-time output port, output data must be set to the RTBL0 and RTBH0 registers before a
4 bits × 1 channel,
2 bits × 1 channel
6 bits × 1 channel
The RTBL0 and RTBH0 registers are 4-bit registers that hold preset output data.
These registers are mapped to different addresses in the peripheral I/O register area.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
If an operation mode of 4 bits × 1 channel or 2 bits × 1 channel is specified (RTPC0.BYTE0 bit = 0), data can
be individually set to the RTBL0 and RTBH0 registers. The data of both these registers can be read at once
by specifying the address of either of these registers.
If an operation mode of 6 bits × 1 channel is specified (BYTE0 bit = 1), 8-bit data can be set to both the RTBL0
and RTBH0 registers by writing the data to either of these registers. Moreover, the data of both these
registers can be read at once by specifying the address of either of these registers.
Table 13-2 shows the operation when the RTBL0 and RTBH0 registers are manipulated.
Operation Mode
real-time output trigger is generated.
RTBL0
RTBH0
Cautions 1. When writing to bits 6 and 7 of the RTBH0 register, always set 0.
After reset: 00H
Table 13-2. Operation During Manipulation of RTBL0 and RTBH0 Registers
2. If the RTBL0 and RTBH0 registers are accessed in the following statuses, a
RTBL0
RTBH0
RTBL0
RTBH0
0
Register to Be
Manipulated
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO)
wait will occur. Once the system enters the wait status, the only way to cancel
the wait status is to execute a reset. For details, see 3.4.9 (1) Accessing
special on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillator clock
stopped
R/W
0
Address: RTBL0 FFFFF6E0H, RTBH0 FFFFF6E2H
User’s Manual U18953EJ5V0UD
RTBH05 RTBH04
RTBH0
RTBH0
RTBH0
RTBH0
Higher 4 Bits
Read
RTBL0
RTBL0
RTBL0
RTBL0
RTBL03 RTBL02
Lower 4 Bits
Invalid
RTBH0
RTBH0
RTBH0
Higher 4 Bits
RTBL01
RTBL00
Write
RTBL0
Invalid
RTBL0
RTBL0
Note
Lower 4 Bits