UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 781

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(4) DMA transfer initialization procedure (setting DCHCn.INITn bit to 1)
Even if the INITn bit is set to 1 when the channel executing DMA transfer is to be initialized, the channel may
not be initialized. To definitely initialize the channel, execute either of the following two procedures.
(a) Temporarily stop transfer on all DMA channels
Initialize the channel executing DMA transfer using the procedure in <1> to <7> below.
Note, however, that TCn bit is cleared to 0 when step <5> is executed. Make sure that the other
processing programs do not expect that the TCn bit is 1.
<1> Disable interrupts (DI).
<2> Read the DCHCn.Enn bit for DMA channels other than the one to be forcibly terminated, and transfer
<3> Clear the Enn bit for the DMA channels used (including the channel to be forcibly terminated) to 0. To
<4> Write 04H to DCHCn corresponding to the channel to be forcibly terminated (set the INITn bit to 1).
<5> Read the TCn bit of each channel not to be forcibly terminated. If both the TCn bit and the Enn bit
<6> After the operation in <5>, write the Enn bit value to the DCHCn register.
<7> Enable interrupts (EI).
Cautions 1. Be sure to execute step <5> above to prevent illegal setting of the Enn bit of the
the value to a general-purpose register.
clear the Enn bit for the last DMA channel, execute the clear instruction twice. If the DMA transfer
source or destination is the internal RAM, execute the instruction three times.
read in <2> are 1 (logical product (AND) is 1), clear the saved Enn bit to 0.
Example: Execute instructions in the following order if channels 0, 1, and 2 are used (if the internal
2. Clearing the Enn bit to 0 (<3>) and setting the INITn bit to 1 (<4>) by using a bit
channels on which DMA transfer has been normally completed between <2> and <3>.
manipulation instruction clears the TCn bit, so a bit manipulation instruction must not
be used.
RAM is not the transfer source or destination).
• Write 00H to DCHC0 (clear the E00 bit to 0).
• Write 00H to DCHC1 (clear the E11 bit to 0).
• Write 00H to DCHC2 (clear the E22 bit to 0).
• Write 00H to DCHC2 again (clear the E22 bit to 0).
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER)
User’s Manual U18953EJ5V0UD
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