UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 308

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UPD70F3738GF-GAS-AX

Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3738GF-GAS-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
306
• Capture operation
When the TPnCE bit is set to 1, the 16-bit counter starts incrementing. When it is detected that a valid edge as
been input to the TIPna pin, the value of the 16-bit counter is stored in the TPnCCRa register, and a capture
interrupt request signal (INTTPnCCa) is generated.
The 16-bit counter continues incrementing in synchronization with the count clock. When the counter reaches
FFFFH, it generates an overflow interrupt request signal (INTTPnOV) at the next clock, is cleared to 0000H, and
continues incrementing. At this time, the overflow flag (the TPnOPT0.TPnOVF bit) is also set to 1. The overflow
flag must be cleared to 0 by executing a CLR1 software instruction.
Remark
Figure 7-54. Basic Timing of Operations in Free-Running Timer Mode (Capture Function)
Remark
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
INTTPnOV signal
TIPn0 pin input
TIPn1 pin input
a = 0, 1
n = 0 to 5
16-bit counter
TPnOVF bit
TPnCE bit
The valid edge is the rising edge.
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
User’s Manual U18953EJ5V0UD
D
00
D
CLR1 instruction
Cleared to 0 by
10
D
00
D
D
01
10
D
CLR1 instruction
11
Cleared to 0 by
D
D
01
02
D
11
D
12
CLR1 instruction
Cleared to 0 by
D
02
D
D
03
12
D
13
D
03
D
13

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