UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 571

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Cautions 1. Be sure to read the UAnRX register even when a reception error occurs. If the UAnRX register
2. Reception is performed assuming that there is only one stop bit. A second stop bit is ignored.
3. When reception is completed, read the UAnRX register after the reception complete interrupt
4. If the receive completion processing (INTUAnR signal generation) of UARTAn conflicts with
is not read, an overrun error occurs during reception of the next data, and reception errors
continue occurring indefinitely.
request signal (INTUAnR) has been generated, and clear the UAnRXE bit to 0. If the UAnRXE
bit is cleared to 0 before the INTUAnR signal is generated, the read value of the UAnRX
register cannot be guaranteed.
setting the UAnPWR bit or UAnRXE bit to 0, the INTUAnR signal may be generated in spite of
there being no data stored in the UAnRX register.
To complete reception without waiting for INTUAnR signal generation, be sure to clear (0) the
interrupt request flag (UAnRIF) of the UAnRIC register, after setting (1) the interrupt mask flag
(UAnRMK) of the interrupt control register (UAnRIC) and then set (1) the UAnPWR bit or
UAnRXE bit to 0.
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
User’s Manual U18953EJ5V0UD
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