UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 822

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.8 Interrupt Response Time of CPU
request signals successively, input the next interrupt request signal at least 5 clock cycles after the preceding interrupt.
820
Except for the following cases, the interrupt response time of the CPU is at least 4 clock cycles. To input interrupt
• In IDLE1/IDLE2/STOP mode
• When the external bus is accessed
• When interrupt request non-sample instructions are successively executed (see 21.9
• When an interrupt control register is accessed
(1) Minimum interrupt response time
(2) Maximum interrupt response time
Remark
Minimum
Maximum
Interrupts Are Not Acknowledged by CPU.)
Interrupt response time (internal system clock cycles)
Instruction (first instruction of interrupt service routine)
Instruction (first instruction of interrupt service routine)
Figure 21-16. Pipeline Operation When Interrupt Request Signal Is Acknowledged (Outline)
INT1 to INT4: Interrupt acknowledgment processing
IFX:
IDX:
Internal interrupt
CHAPTER 21 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION
Interrupt acknowledgment operation
Interrupt acknowledgment operation
4
6
Invalid instruction fetch
Invalid instruction decode
Analog delay time
Analog delay time
External interrupt
Interrupt request
Interrupt request
Internal clock
Instruction 1
Instruction 2
4 +
6 +
Internal clock
Instruction 1
Instruction 2
User’s Manual U18953EJ5V0UD
The following cases are exceptions.
• In IDLE1/IDLE2/STOP mode
• External bus access
• Two or more interrupt request non-sample instructions are
• Access to peripheral I/O register
executed in succession
IF
IF
INT1 INT2 INT3 INT3 INT3 INT4
IFX IDX
ID
INT1 INT2 INT3 INT4
IFX IDX
ID
4 system clock cycles
EX MEM MEM MEM WB
6 system clock cycles
EX MEM WB
Conditions
IF
ID
IF
Periods in Which
EX
ID
EX