UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 315

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UPD70F3738GF-GAS-AX

Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3738GF-GAS-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(2) Using free-running timer mode
(a) Interval operation using the TPnCCRa register as a compare register
When TMPn is used as an interval timer with the TPnCCRa register used as a compare register, the
comparison value at which the next interrupt request signal is generated each time the INTTPnCCa signal
has been detected must be set by software.
(CCR1 buffer register)
When performing an interval operation in the free-running timer mode, two intervals can be set for one
channel.
To perform the interval operation, the value of the corresponding TPnCCRa register must be set again in
the interrupt servicing that is executed when the INTTPnCCa signal is detected.
The value to be set in this case can be calculated by the following expression, where “D
period.
(CCR0 buffer register)
Compare register default value: D
Value set to compare register second and subsequent time: Previous set value + D
(If the calculation result is greater than FFFFH, subtract 10000H from the result and set the register to
this value.)
Remark
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR1 register
TPnCCR0 register
TOPn1 pin output
TOPn pin output
16-bit counter
Figure 7-58. Interval Operation of TMPn in Free-Running Timer Mode
TPnCE bit
FFFFH
a = 0, 1
n = 0 to 5
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Interval period
Interval period
D
(D
(D
00
User’s Manual U18953EJ5V0UD
00
D
10
D
+ 1)
a
10
+ 1)
D
00
− 1
10
Interval period
(10000H +
D
01
Interval period
− D
(10000H +
D
D
D
00
11
)
01
01
− D
D
Interval period
10
D
11
(D
)
11
02
− D
D
Interval period
02
01
D
(10000H +
)
D
02
12
Interval period
− D
(10000H +
D
D
D
11
03
12
)
12
− D
D
03
02
D
)
Interval period
03
(10000H +
D
Interval period
13
(10000H +
D
− D
04
D
− D
12
D
13
)
D
13
03
04
)
D
a
04
D
D
14
05
a
” is the interval
313

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