UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 94

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.4.9
92
16-bit timer/event counter P (TMP)
(n = 0 to 5)
16-bit timer/event counter Q (TMQ)
Watchdog timer 2 (WDT2)
Real-time output function (RTO)
A/D converter
I
CRC
2
C00 to I
(1) Accessing special on-chip peripheral I/O registers
This product has two types of internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware.
The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and
an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. If there is
a possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is
accessed, so that correct data is transferred. As a result, the CPU does not start processing of the next
instruction but enters the wait status. If this wait status occurs, the number of clocks required to execute an
instruction increases by the number of wait clocks shown below.
This must be taken into consideration if real-time processing is required.
When special on-chip peripheral I/O registers are accessed, more wait states may be required in addition to
the wait states set by the VSWC register.
The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks)
at this time are shown below.
Number of clocks necessary for access = 3 + i + j + (2 + j) × k
Caution Accessing the above registers is prohibited in the following statuses. If a wait cycle is
Remark
Cautions
Peripheral Function
2
C02
generated, it can only be cleared by a reset.
• When the CPU operates on the subclock and main clock oscillation is stopped
• When the CPU operates on the internal oscillator clock
i: Value (0) of higher 4 bits of VSWC register
j: Value (0 or 1) of lower 4 bits of VSWC register
TPnCNT
TPnCCR0, TPnCCR1
TQ0CNT
TQ0CCR0 to TQ0CCR3
WDTM2
RTBL0, RTBH0
ADA0M0
ADA0CR0 to ADA0CR11
ADA0CR0H to ADA0CR11H
IICS0 to IICS2
CRCD
Table 3-3. Registers That Requires Waits
Register Name
CHAPTER 3 CPU FUNCTION
User’s Manual U18953EJ5V0UD
Read
Write
Read
Read
Write
Read
Write
(when WDT2 operating)
Write
(RTPC0.RTPOE0 bit = 0)
Read
Read
Read
Read
Write
Access
1 or 2
1 or 2
1 or 2
1
1 or 2
• 1
• Continuous write: 3 or 4
1 or 2
1 or 2
• 1
• Continuous write: 3 or 4
1 or 2
3
1
1
st
st
access: No wait
access: No wait
k