UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 823

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.9 Periods in Which Interrupts Are Not Acknowledged by CPU
acknowledged between an interrupt request non-sample instruction and the next instruction (the interrupt is held
pending).
21.10 Cautions
21.10.1 Restored PC
starts.
instructions, the execution of that instruction stops and resumes following completion of interrupt servicing.
An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be
The interrupt request non-sample instructions are as follows.
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instruction (for PSW)
• The store instruction for the PRCMD register
• The store, SET1, NOT1, or CLR1 instructions for the following registers.
Restored PC is the value of the program counter (PC) saved to EIPC, FEPC, or DBPC when interrupt servicing
• Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W)
• Divide instructions (DIV, DIVH, DIVU, DIVHU)
• PREPARE, DISPOSE instructions (only when an interrupt occurs before the stack pointer is updated)
• Interrupt-related registers:
• Power save control register (PSC)
• On-chip debug mode register (OCDM)
Remarks 1. xx: Identification name of each peripheral unit (see Table 21-3 Interrupt Control Registers
Interrupt control register (xxICn), interrupt mask registers 0 to 3 (IMR0 to IMR3)
If a non-maskable or maskable interrupt is acknowledged during the execution of any of the following
2. For details about the operation of the pipeline, see the V850ES Architecture User's Manual
(U15943E).
n:
CHAPTER 21 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION
(xxICn))
Peripheral unit number (see Table 21-3 Interrupt Control Registers (xxICn)).
User’s Manual U18953EJ5V0UD
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