UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 766

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

764
(5) DMA channel control registers 0 to 3 (DCHC0 to DCHC3)
Notes 1. The TCn bit is read-only.
Cautions 1. Be sure to clear bits 6 to 3 of the DCHCn register to 0.
The DCHC0 to DCHC3 registers are 8-bit registers that control DMA transfer for DMA channel n.
These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read-only and bits 1 and 2 are
write-only. If bit 1 or 2 is read, the value read is always 0.)
Reset sets these registers to 00H.
2. The INITn and STGn bits are write-only.
2. When DMA transfer is completed (when a terminal count is generated), the Enn bit is
(n = 0 to 3)
DCHCn
cleared to 0 and then the TCn bit is set to 1. If the DCHCn register is read while its bits are
being updated, a value indicating “transfer not completed and transfer is disabled” (TCn bit
= 0 and Enn bit = 0) may be read.
After reset:
INITn
STGn
TCn
TCn
This bit is set to 1 at the last DMA transfer and cleared to 0 when it is read.
DMA transfer is enabled when the Enn bit is set to 1.
When DMA transfer is completed (when a terminal count is generated), this bit is
automatically cleared to 0.
To abort DMA transfer, clear the Enn bit to 0 by software. To resume DMA transfer,
set the Enn bit to 1 again.
When aborting or resuming DMA transfer, be sure to follow the procedure described
in 18.13 (5) Procedure for temporarily stopping DMA transfer.
00H
Enn
<7>
0
1
0
1
Note 1
Note 1
Note 2
Note 2
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER)
DMA transfer is not complete.
DMA transfer is complete.
If the INITn bit is set to 1 with DMA transfer disabled (Enn bit = 0), the
DMA transfer status can be initialized.
This is a software startup trigger for DMA transfer.
If this bit is set to 1 in the DMA transfer enabled state (TCn bit = 0, Enn
bit = 1), DMA transfer is started.
DMA transfer disabled
DMA transfer enabled
R/W
0
6
User’s Manual U18953EJ5V0UD
Address:
0
5
DMA channel n is to be enabled or disabled
Status flag indicating whether DMA transfer
Setting of whether DMA transfer via
DCHC0 FFFFF0E0H, DCHC1 FFFFF0E2H,
DCHC2 FFFFF0E4H, DCHC3 FFFFF0E6H
via DMA channel n is complete
0
4
3
0
INITn
<2>
Note 2
STGn
<1>
Note 2
Enn
<0>