UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 258

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

with the count clock, and the counter starts incrementing. At this time, the output of the TOPn0 pin is inverted and the
set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
0000H, the output of the TOPn0 pin is inverted, and a compare match interrupt request signal (INTTPnCC0) is
generated.
256
TPnCTL1
When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization
When the value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to
The interval can be calculated by using the following expression:
An example of the register settings when the interval timer mode is used is shown in the figure below.
Interval = (Set value of TPnCCR0 register + 1) × Count clock cycle
Remark
(a) TMPn control register 0 (TPnCTL0)
(b) TMPn control register 1 (TPnCTL1)
TPnCTL0
Note The TPnEEE bit can only be set to 1 when the timer output (TOPn1) is used. Note that when
0
n = 0 to 5
setting the TPnEEE bit to 1, the TPnCCR0 and TPnCCR1 registers must be set to the same
value (that is, the same value as the value already specified for these registers). (For details, see
7.4.1 (2) (d) Operation of TPnCCR1 register.)
TPnCE
0/1
TPnEST
0
Figure 7-8. Register Settings in Interval Timer Mode (1/2)
TPnEEE
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
0/1
Note
0
0
User’s Manual U18953EJ5V0UD
0
0
TPnMD2 TPnMD1 TPnMD0
0
0
TPnCKS2 TPnCKS1 TPnCKS0
0/1
0
0/1
0
0, 0, 0:
Interval timer mode
0: Increment TMPn based on
1: Increment TMPn based on the
0/1
the count clock selected by
the TPnCKS0 to TPnCKS2 bits.
input of an external event
count signal.
These bits select
the count clock.
0: Stop counting
1: Enable counting