UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 310

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

308
TPnOPT0
TPnIOC1
TPnIOC2
(d) TMPn I/O control register 1 (TPnIOC1)
(e) TMPn I/O control register 2 (TPnIOC2)
(f) TMPn option register 0 (TPnOPT0)
(g) TMPn counter read buffer register (TPnCNT)
(h) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1)
The value of the 16-bit counter can be read by reading this register.
These registers function as capture registers or compare registers according to the setting of the
TPnOPT0.TPnCCSa bit.
When the registers function as capture registers, they store the value of the 16-bit counter when it is
detected that a valid edge has been input to the TIPna pin, after which the INTTPnCCa signal is
generated.
When the registers function as compare registers and when the TPnCCRa register is set to Da, the
INTTPnCCa signal is generated the when the counter reaches (D
TOPna pin is inverted.
Remark
0
0
0
a = 0, 1
n = 0 to 5
Figure 7-55. Register Settings in Free-Running Timer Mode (2/2)
0
0
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
TPnCCS1
0/1
0
0
TPnCCS0
0/1
0
0
User’s Manual U18953EJ5V0UD
TPnEES1
TPnIS3
0/1
0/1
0
TPnEES0 TPnETS1 TPnETS0
TPnIS2
0/1
0/1
0
TPnIS1
0/1
0
0
a
+ 1), and the output signal of the
TPnOVF
TPnIS0
0/1
0/1
0
These bits select the valid
edge of the TIPn1 pin input.
These bits select the valid
edge of the external event
count input.
These bits select the valid
edge of the TIPn0 pin input.
Overflow flag
Specifies whether TPnCCR0
register is used for capture
or compare.
Specifies whether TPnCCR1
register is used for capture
or compare.