UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 878

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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24.5 Cautions
immediately after the reset ends. The usable range of the internal operating frequency of the V850ES/JG3-L depends
on the supply voltage (2.5 MHz (MAX.) @ 2.0 to 2.2 V or 5 MHz (MAX.) @ 2.2 to 2.7 V or 20 MHz (MAX.) @ 2.7 to 3.6
V).
876
When executing a power-on reset operation, the supply voltage must be within the guaranteed operating range
(1) At less than 2.0 V immediately after reset ends
(2) At 2.0 V or more to less than 2.2 V immediately after reset ends (
(3) At 2.2 V or more to less than 2.7 V immediately after reset ends
(4) At 2.7 to 3.6 V immediately after reset ends
Use prohibited
• Inputting 2.5 MHz or more to the main clock oscillator is prohibited.
• Be sure to stop the PLL (PLLCTL.PLLON = 0) in the initialization routine.
μ
• Input f
• Inputting 5 MHz or more to the main clock oscillator is prohibited.
• Be sure to stop the PLL (PLLCTL.PLLON = 0) in the initialization routine.
• Both the clock-through mode and PLL mode can be used.
Remarks 1. The voltage value (V) is the value of V
• Input f
PD70F3737, 70F3738 cannot be used.
X
X
= 2.5 to 5 MHz to the main clock oscillator and set the clock-through mode (PLLCTL.SELPLL = 0).
= 2.5 MHz to the main clock oscillator and set the clock-through mode (PLLCTL.SELPLL = 0).
2. A reset ends at the following timing. For the relationship between the rising of V
reset signal generated by the RESET pin ends, see 32.7.4 Power on/power off/reset timing
and 33.7.4 Power on/power off/reset timing.
RESET
V
DD
CHAPTER 24 RESET FUNCTION
User’s Manual U18953EJ5V0UD
DD
.
Reset ends
μ
PD70F3792, 70F3793 only)
DD
and when the