UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 204

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.8
5.8.1
the external address/data bus goes into a high-impedance state, the HLDAK signal is asserted (low level), and the
bus is released (bus hold status).
deasserted (high level), driving these signals is started again.
an on-chip peripheral I/O register or the external memory is accessed.
exist.
or a bit manipulation instruction. The timing at which a bus hold request is not acknowledged is shown below.
202
CPU bus lock
Read-modify-write access by bit
manipulation instruction
The HLDRQ and HLDAK signals are valid if the PCM2 and PCM3 pins are set to the control mode.
When the HLDRQ signal is asserted (low level), indicating that another bus master has requested bus mastership,
During the bus hold period, the CPU continues executing the program in the internal ROM and internal RAM until
The bus hold function enables the configuration of multi-processor type systems in which two or more bus masters
Note that a bus hold request is not acknowledged during a multiple-access cycle initiated by the bus sizing function
Bus Hold Function
Functional outline
Status
Table 5-6. Timing at Which Bus Hold Request Is Not Acknowledged
16 bits
8 bits
Data Bus
Width
If the request for the bus mastership is cleared and the HLDRQ signal is
CHAPTER 5 BUS CONTROL FUNCTION
−
User’s Manual U18953EJ5V0UD
Word access to even address
Word access to odd address
Halfword access to odd address
Word access
Halfword access
Access Type
−
Between first and second access
Between first and second access
Between second and third access
Between first and second access
Between first and second access
Between second and third access
Between third and fourth access
Between first and second access
Between read access and write access
Timing at Which Bus Hold Request Is
Not Acknowledged