UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1010

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1008
The communication reservation flowchart is illustrated below.
(Communication reservation)
Note The communication reservation operation executes a write to the IICn register when a stop
Remark
condition interrupt request occurs.
n = 0 to 3 (V850ES/JH3-E)
n = 0 to 4 (V850ES/JJ3-E)
Figure 20-18. Communication Reservation Flowchart
Yes
Note
Cancel communication
reservation
Define communication
reservation
IICn register
MSTSn bit = 0?
SET1 STTn
Wait
DI
EI
User’s Manual U19601EJ2V0UD
No
(Generate start condition)
CHAPTER 20 I
←
xxH
2
C BUS
Sets STTn bit (communication reservation).
Defines that communication reservation is in effect
(defines and sets user flag to any RAM).
Secures wait period set by software (see Table 20-6).
Confirmation of communication reservation
Clears user flag.
IICn register write operation