UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 188

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes 1. KR6 and TIT00 are alternate functions. When using the pin for the TIT00 function, disable key return detection of KR6, which is the alternate function (set the
P96
P97
P98
P99
Pin Name
2. When using as the A0 to A15 pins, be sure to set all 16 bits of the PMC9 register to FFFFH at once.
3. KR7 and TIT01 are alternate functions. When using the pin for the TIT01 function, disable key return detection of KR7, which is the alternate function (set the
4. The SIE1 function is assigned to the PDH0 pin as well as the P99 pin. When using the P99 pin for the SIE1 function, do not specify the PDH0 pin to be used
KRM.KRM6 bit to 0). Also, when using the pin for the KR6 function, disable edge detection of TIT00, which is the alternate function (set the TTI0IOC1.TT0IS1
and TT0IS0 bits to 00).
KRM.KRM7 bit to 0). Also, when using the pin for the KR7 function, disable edge detection of TIT01, which is the alternate function (set the TTI0IOC1.TT0IS3
and TT0IS2 bits to 00).
for this function.
TECR0
TIT00
KR6
TOT00
A6
TENC00
TIT01
KR7
TOT01
A7
TENC01
INTP17
A8
SIE1
TXDC5
SDA03
A9
Alternate Function
Note 2
Note 2
Note 2
Note 2
Name
Note 1
Note 3
Note 4
Note 1
Note 3
Input
Input
Input
Output
Output
Input
Input
Input
Output
Output
Input
Input
Output
Input
Output
I/O
Output
I/O
P96 = Setting not required PM96 = Setting not required PMC96 = 1
P96 = Setting not required PM96 = Setting not required PMC96 = 1
P96 = Setting not required PM96 = Setting not required PMC96 = 1
P96 = Setting not required PM96 = Setting not required PMC96 = 1
P96 = Setting not required PM96 = Setting not required PMC96 = 1
P97 = Setting not required PM97 = Setting not required PMC97 = 1
P97 = Setting not required PM97 = Setting not required PMC97 = 1
P97 = Setting not required PM97 = Setting not required PMC97 = 1
P97 = Setting not required PM97 = Setting not required PMC97 = 1
P97 = Setting not required PM97 = Setting not required PMC97 = 1
P98 = Setting not required PM98 = Setting not required PMC98 = 1
P98 = Setting not required PM98 = Setting not required PMC98 = 1
P98 = Setting not required PM98 = Setting not required PMC98 = 1
P99 = Setting not required PM99 = Setting not required PMC99 = 1
P99 = Setting not required PM99 = Setting not required PMC99 = 1
P99 = Setting not required PM99 = Setting not required PMC99 = 1
P99 = Setting not required PM99 = Setting not required PMC99 = 1
Pn Register
Pnx Bit of
Table 4-18. Using Port Pin as Alternate-Function Pin (9/13)
PMn Register
PMnx Bit of
PMCn Register
PMCnx Bit of
PFCE96 = 0
PFCE96 = 1
PFCE96 = 1
PFCE96 = 1
PFCE96 = 1
PFCE97 = 0
PFCE97 = 0
PFCE97 = 0
PFCE97 = 1
PFCE97 = 1
PFCE98 = 0
PFCE98 = 0
PFCE98 = 1
PFCE99 = 0
PFCE99 = 0
PFCE99 = 1
PFCE99 = 1
PFCEn Register
PFCEnx Bit of
PFC96 = 0
PFC96 = 0
PFC96 = 0
PFC96 = 0
PFC96 = 0
PFC97 = 0
PFC97 = 1
PFC97 = 1
PFC97 = 0
PFC97 = 1
PFC98 = 0
PFC98 = 1
PFC98 = 0
PFC99 = 0
PFC99 = 1
PFC99 = 0
PFC99 = 1
PFCn Register
PFCnx Bit of
KRM6 (KRM) = 0
TT0IS1, TT0IS0 (TTI0IOC1) = 0
Note 2
KRM7 (KRM) = 0
TT0IS3, TT0IS2 (TTI0IOC1) = 0
(Registers)
Other Bits