UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 739

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(10) UARTBn receive data register AP (UBnRXAP), UARTBn receive data register (UBnRX)
(11) Transmit shift register
The receive data register holds receive data. In the single mode, the 8-bit × 1-stage UBnRX register is used.
The 16-bit × 16-stage receive FIFO (UBnRXAP register) is used in the FIFO mode.
The receive data is stored in the lower 8 bits of the receive FIFO (UBnRXAP register) and the error
information of the received data is stored in the higher 8 bits (bit 8 and bit 9). If a reception error (such as a
parity error or a framing error) occurs in the FIFO mode, the error data can be identified by reading the
UBnRXAP register in 16-bit (halfword) units (error information is appended as UBnPEF bit = 1 or UBnFEF bit
= 1). When the lower 8 bits of the UBnRXAP register are read in 8-bit (byte) units, the higher 8 bits are
discarded. Therefore, if no error has occurred, only the receive data of the UBnRXAP register can be read
successively by being read in 8-bit (byte) units in the same way as the UBnRX register.
When 7-bit length data is received with the LSB first, the received data is transferred to bits 6 to 0 of the
receive data register from the LSB (bit 0), with the MSB (bit 7) always being 0. When data is received with
the MSB first, the received data is transferred to bits 7 to 1 of the receive data register from the MSB (bit 7),
with the LSB (bit 0) always being 0. If an overrun error occurs, the receive data at that time is not transferred
to the receive data register.
While reception is enabled, the received data is transferred from the receive shift register to the receive data
register, in synchronization with the shift-in processing of one frame.
A reception end interrupt request signal (INTUBnTIR) is generated by transferring the data to the UBnRX
register in the single mode, or transferring the number of receive data set as the trigger by the
UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits to receive FIFO in the FIFO mode. If data is stored in receive
FIFO when the next data does not come (start bit is not detected) after the next data reception wait time
specified by the UBnFIC1.UBnTC4 to UBnFIC1.UBnTC0 bits has elapsed in the FIFO mode, a reception
timeout interrupt request signal (INTUBnTITO) is generated.
This is a shift register that converts the parallel data that was transferred from the transmit data register into
serial data.
When one byte of data is transferred from the transmit data register, the transmit shift register data is output
from the TXDBn pin.
This register cannot be directly manipulated.
Remark
n = 0, 1
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
User’s Manual U19601EJ2V0UD
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