UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1446

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1444
26 to 16
10 to 0
(3) FLOWTHRESH: Flow control threshold value register
Bit
This register is used to set threshold values of the receive FIFO at which flow control and zero pause control
frame transmission are started.
Access
Address
Default value 0600 0200H. This register is cleared to its default value by all types of resets.
Caution Be sure to set bits 31 to 27 and 15 to 11 to “0”.
FLOWTHR7 FLOWTHR6 FLOWTHR5 FLOWTHR4 FLOWTHR3
FLOWTHR
[10:0]
ZPTHR[10:0] These bits set in bytes the threshold value of zero pause control packet transmission.
ZPTHR7
R/W
R/W
31
23
15
Name
R
R
0
0
7
This register can be read and written in 32-bit units.
002E 0218H
ZPTHR6
These bits specify in bytes the threshold value of the receive FIFO at which flow control is started.
Flow control is started when the amount of data in the receive FIFO reaches to the value set to
these bits. Back pressure transmission is executed in the half-duplex mode and pause control
packets are transmitted in the full-duplex mode. Writing bits 17 and 16 is ignored because the
receive FIFO can only be written in 32-bit (4-byte) units.
When bits 17 and 16 are read, 0 is always returned for each bit.
When zero pause packet transmission is enabled by setting the MFFCNT.ZEROPAUSE bit to 1
(high level) and flow is controlled by pause control packets, the zero pause packet is transmitted
when the amount of data in the receive FIFO falls below the threshold value set to these bits.
Writing bits 1 and 0 is ignored because the receive FIFO can only be written in 32-bit (4-byte)
units.
When bits 1 and 0 are read, 0 is always returned for each bit.
R/W
R/W
30
22
14
R
R
0
0
6
ZPTHR5
CHAPTER 23 ETHERNET CONTROLLER
R/W
R/W
29
21
13
R
R
0
0
5
User’s Manual U19601EJ2V0UD
ZPTHR4
R/W
R/W
28
20
12
R
R
0
0
4
ZPTHR3
R/W
R/W
27
19
11
R
R
0
0
3
Description
FLOWTHR10 FLOWTHR9 FLOWTHR8
FLOWTHR2
ZPTHR10
ZPTHR2
R/W
R/W
R/W
R/W
26
18
10
2
FLOWTHR1 FLOWTHR0
ZPTHR9
ZPTHR1
R/W
R/W
25
17
R
R
9
1
ZPTHR8
ZPTHR0
R/W
R/W
24
16
R
R
8
0