UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1494

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
1492
(2) Areas accessible by DMA transfer
(3) DMA address boundary
(4) DMA arbitration
The areas subject to DMA transfer are shown below.
With the DMAC of in the Ethernet controller, the address boundary does not have to be considered when
setting the start address of the data buffer and the number of transfer bytes.
If there is fractional data during burst transfer, the fraction is automatically processed before the data is
transferred.
However, because it is not possible to predict where the data to be received will end, the last transfer may be a
dummy transfer when burst transfer is used.
Remark
Because the Ethernet controller supports full-duplex transfer, DMA transmission and DMA reception may be
executed together. If DMA requests for transmission and reception are made at the same time, the request for
reception takes precedence.
Internal ROM
inaccessible
When the 4-, 8-, or 16-beat transfer mode is used, the last data that falls short of a fixed length is
automatically transferred in undefined length mode.
Byte access for byte alignment is always executed in the single transfer mode.
Table 23-6. Areas Subject to Transfer by DMAC in Ethernet Controller
Internal RAM
inaccessible
CHAPTER 23 ETHERNET CONTROLLER
User’s Manual U19601EJ2V0UD
Accessible
Data RAM
External Memory
Accessible
On-chip Peripheral I/O
Inaccessible

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