UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 210

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
<R>
5.5
5.5.1
208
(1) Data wait control register 0 (DWC0)
Wait Function
To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus
cycle that is executed for each CS space.
The number of wait states can be programmed by using the DWC0 register. Immediately after system reset, 7
data wait states are inserted for all the blocks.
The DWC0 register can be read or written in 16-bit units.
Reset sets this register to 7777H.
Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are
Notes 1. V850ES/JJ3-E only. Be sure to set 1 in the V850ES/JH3-E.
Caution Be sure to set bits 15, 11, 7, and 3 to “0”.
Programmable wait function
2. The DW12 to DW10 bits set wait of access to the USB function area.
DWC0
2. Write to the DWC0 register after reset, and then do not change the set values. Also, do
After reset:
It is recommended to set the DW12 to DW10 bits to 001B (1 wait).
always accessed without a wait state. The on-chip peripheral I/O area is also not subject
to programmable wait, and only wait control from each peripheral function is performed.
not access an external memory area until the initial settings of the DWC0 register are
complete.
DWn2
15
7777H
0
7
0
0
0
0
0
1
1
1
1
DW32
DW12
DWn1
14
0
0
1
1
0
0
1
1
6
R/W
CHAPTER 5 BUS CONTROL FUNCTION
Note1
Note2
DW31
DW11
DWn0
User’s Manual U19601EJ2V0UD
CS3
Address:
13
5
0
1
0
1
0
1
0
1
Note1
Note2
DW30
DW10
None
1
2
3
4
5
6
7
FFFFF484H
12
4
Note1
Note2
Number of wait states inserted in
11
0
0
CSn space (n = 0 to 3)
3
DW22
DW02
10
2
DW21
DW01
CS0
CS2
1
9
DW20
DW00
0
8

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