UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1137

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.11.2 CAN stop mode
CAN module can enter the CAN stop mode only from the CAN sleep mode. Release of the CAN stop mode puts the
CAN module in the CAN sleep mode.
and C0CTRL.PSMODE0 bits and not by a change in the CAN bus state. No message is transmitted even when
transmission requests are issued or pending.
The CAN stop mode can be used to set the CAN controller to standby mode to reduce power consumption. The
The CAN stop mode can only be released (shifting to CAN sleep mode) by writing 01B to the C0CTRL.PSMODE1
(1) Entering CAN stop mode
(2) Status in CAN stop mode
(3) Releasing CAN stop mode
A CAN stop mode transition request is issued by writing 11B to the PSMODE1 and PSMODE0 bits.
A CAN stop mode request is only acknowledged when the CAN module is in the CAN sleep mode. In all other
modes, the request is ignored.
Caution To set the CAN module to the CAN stop mode, the module must be in the CAN sleep mode.
The CAN module is in one of the following states after it enters the CAN stop mode.
• The internal operating clock is stopped and the power consumption is minimized.
• To wake up the CAN module from the CPU, data can be written to the PSMODE1 and PSMODE0 bits, but
• The CAN0 module registers can be read, except for the C0LIPT, C0RGPT, C0LOPT, and C0TGPT registers.
• The CAN0 message buffer registers cannot be written or read.
• The C0GMCTRL.MBON bit is cleared to 0.
• An initialization mode transition request is not acknowledged and is ignored.
The CAN stop mode can only be released by writing 01B to the PSMODE1 and PSMODE0 bits. After
releasing the CAN stop mode, the CAN module enters the CAN sleep mode.
When the initialization mode is requested while the CAN module is in the CAN stop mode, that request is
ignored; the CPU has to release the stop mode and subsequently the CAN sleep mode before entering into
initialization mode. It is impossible to enter another operation mode directly from the CAN stop mode without
entering the CAN sleep mode, the request will be ignored.
nothing can be written to other CAN0 module registers or bits.
To confirm that the module is in the sleep mode, check that the PSMODE1 and PSMODE0
bits = 01B, and then request the CAN stop mode. If a bus change occurs at the CAN
reception pin (CRXD0) while this process is being performed, the CAN sleep mode is
automatically released.
acknowledged (while the CAN clock is supplied, however, the PSMODE0 must be cleared by
software after the bus level of the CAN reception pin (CRXD0) is changed).
CHAPTER 21 CAN CONTROLLER
User’s Manual U19601EJ2V0UD
In this case, the CAN stop mode transition request cannot be
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