UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1468

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
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1466
15 to 0
(20) TXABTCNT: Transmission abort counter
Bit
This is a transmission abort counter.
transmission error (including an underrun).
Access
Address
Default value 0000 0000H. This register is cleared to its default value by all types of resets.
Caution Be sure to set bits 31 to 16 to “1”.
TABCNT15 TABCNT14 TABCNT13 TABCNT12 TABCNT11 TABCNT10 TABCNT9
TABCNT7
TABCNT
[15:0]
R/W
R/W
31
23
15
Name
R
R
0
0
7
This register can be read and written in 32-bit units.
002E 0270H
TABCNT6
Transmission abort count
These bits count the number of packets that have resulted in a MAC transmission error (including
an underrun).
This counter is not incremented when MFFCONT.TABT is set to 1 to retransmit an aborted packet.
If MFFCONT.TXTHRC = 1, retransmission is not executed when transmission has been aborted.
In this case, the counter is incremented.
Packets are counted after 68 bytes have been transferred because they are not retransmitted by a
retry request (usually, the MAC does not issue a retry request after 64 bytes have been
transferred).
If the count value overflows, the value of these bits returns to 0 and the FSTATUS.TACOF bit is
set.
These bits are not cleared by resetting the transmission circuit (by setting TFRST and TFFLSH).
R/W
R/W
30
22
14
R
R
0
0
6
TABCNT5
CHAPTER 23 ETHERNET CONTROLLER
R/W
R/W
29
21
13
R
R
0
0
5
User’s Manual U19601EJ2V0UD
TABCNT4
It counts the number of packets that have resulted in a MAC
R/W
R/W
28
20
12
R
R
0
0
4
TABCNT3
R/W
R/W
27
19
11
R
R
0
0
3
Description
TABCNT2
R/W
R/W
26
18
10
R
R
0
0
2
TABCNT1
R/W
R/W
25
17
R
R
0
0
9
1
TABCNT8
TABCNT0
R/W
R/W
24
16
R
R
0
0
8
0

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