UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 839

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(5) Allowable baud rate range during reception
The baud rate error range at the destination that is allowable during reception is shown below.
Caution The baud rate error during reception must be set within the allowable error range using the
As shown in Figure 17-23, the receive data latch timing is determined by the counter set using the UCnCTL2
register following start bit detection. The transmit data can be normally received if up to the last data (stop bit)
can be received in time for this latch timing.
When this is applied to 11-bit reception, the following is the theoretical result.
Remark
FL = (Brate)
Minimum allowable transfer rate: FLmin = 11 × FL −
transfer rate
transfer rate
transfer rate
Maximum
Brate: UARTCn baud rate
k:
FL:
Latch timing margin: 2 clocks
allowable
allowable
Minimum
UARTCn
following equation.
n = 0 to 5 (V850ES/JH3-E)
n = 0 to 7 (V850ES/JJ3-E)
Set value of UCnCTL2.UCnBRS7 to UCnCTL2.UCnBRS0 bits
1-bit data length
−
1
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
Figure 17-23. Allowable Baud Rate Range During Reception
Latch timing
Start bit
Start bit
Start bit
Bit 0
Bit 0
FL
Bit 0
User’s Manual U19601EJ2V0UD
Bit 1
Bit 1
Bit 1
1 data frame (11 × FL)
FLmin
k − 2
2k
FLmax
× FL =
Bit 7
Bit 7
Bit 7
21k + 2
Parity bit
2k
Parity bit
Parity bit
FL
Stop bit
Stop bit
Stop bit
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