UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 554

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

552
(e) Clearing overflow flag
Note The overflow counter is set arbitrarily by software on the internal RAM.
<1> Read the TT0CCRn register (setting of the default value of the TIT0n pin input).
<2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the
<3> An overflow occurs a second time. Increment the overflow counter and clear the overflow flag to 0
<4> Read the TT0CCRn register.
Remark
The overflow flag can be cleared to 0 by clearing the TT0OVF bit to 0 with the CLR instruction after
reading the TT0OVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TT0OPT0 register after
reading the TT0OVF bit when it is 1.
TT0CCRn register
INTTT0OV signal
overflow interrupt servicing.
in the overflow interrupt servicing.
Read the overflow counter.
→ When the overflow counter is “N”, the pulse width can be calculated by (N × 10000H + D
Clear the overflow counter (0H).
TIT0n pin input
16-bit counter
D
In this example, the pulse width is (20000H + D
TT0OVF bit
a0
counter
n = 0, 1
TT0CE bit
).
Overflow
FFFFH
0000H
Note
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Example when capture trigger interval is long
User’s Manual U19601EJ2V0UD
0H
D
a0
<1> <2>
a1
1 cycle of 16-bit counter
– D
a0
Pulse width
) because an overflow occurs twice.
D
1H
a0
<3> <4>
D
a1
2H 0H
D
a1
a1
–