UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1579

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

25.3.4 Interrupt control register (xxICn)
for each maskable interrupt request.
The xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 47H.
Caution Disable interrupts (DI) or mask the interrupt to read the xxICn.xxIFn bit. If the xxIFn bit is read
The addresses and bits of the interrupt control registers are as follows.
Note The flag xxlFn is reset automatically by the hardware if an interrupt request signal is acknowledged.
Remark
while interrupts are enabled (EI) or while the interrupt is unmasked, the correct value may not be
read when acknowledging an interrupt and reading the bit conflict.
xx: Identification name of each peripheral unit (see Table 25-4 Interrupt Control Register (xxICn))
n: Peripheral unit number (see Table 25-4 Interrupt Control Register (xxICn)).
xxICn
After reset:
xxPRn2
xxMKn
CHAPTER 25 INTERRUPT/EXCEPTION PROCESSING FUNCTION
xxIFn
xxIFn
47H
<7>
0
1
0
1
0
0
0
0
1
1
1
1
Interrupt request not issued
Interrupt request issued
Interrupt servicing enabled
Interrupt servicing disabled (pending)
xxPRn1
R/W
xxMKn
<6>
0
0
1
1
0
0
1
1
Address:
xxPRn0
User’s Manual U19601EJ2V0UD
0
0
1
0
1
0
1
0
1
FFFFF112H to FFFFF184H
Specifies level 0 (highest).
Specifies level 1.
Specifies level 2.
Specifies level 3.
Specifies level 4.
Specifies level 5.
Specifies level 6.
Specifies level 7 (lowest).
Interrupt request flag
0
Interrupt mask flag
Interrupt priority specification bit
0
xxPRn2
Note
xxPRn1
xxPRn0
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