UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1636

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

28.3.3 Reset by clock monitor
reset request signal when oscillation of the main clock is stopped.
1634
Main clock oscillator (f
Subclock oscillator (f
Internal oscillator (f
Peripheral clock (f
Internal system clock (f
CPU clock (f
CPU
WDT2
Internal RAM
I/O lines (port pins/alternate-function pins)
On-chip peripheral I/O registers
On-chip peripheral functions other than
above
When the clock monitor is enabled, it samples the main clock by using the internal oscillation clock and generates a
After reset is canceled, the CPU operates using the internal oscillation clock.
Once the CLM.CLME bit is set to 1 (to enable the clock monitor), it can only be cleared by a reset signal.
The clock monitor automatically stops under the following conditions.
• When the oscillation stabilization time after shifting to STOP mode is being counted
• When the main clock is stopped (after setting the PCC.MCK bit to 1 when the system is operating on the
• When the sampling clock (internal oscillation clock) is stopped
• When the CPU is operating on the internal oscillation clock
Remark
subclock and before setting the PCC.CLS bit to 0 when the system is operating on the main clock)
CPU
For the timing of a reset triggered by the clock monitor, see CHAPTER 29 CLOCK MONITOR.
)
Table 28-3. Hardware Status During and After Reset Triggered by Clock Monitor
XX
Item
R
)
to f
XT
X
)
)
XX
XX
),
/1,024)
Oscillation stops
Oscillation continues
Oscillation stops
Operation stops
Operation stops
Initialized
Operation stops (initialized to 0)
Undefined
High impedance
Initialized to the specified status. The OCDM register retains its value.
Operation stops
CHAPTER 28 RESET FUNCTIONS
User’s Manual U19601EJ2V0UD
During Reset
Oscillation starts
Oscillation starts
Operation starts after oscillation
stabilization time has elapsed
Operation starts after oscillation
stabilization time (initialized to f
elapsed
Program execution starts after oscillation
stabilization time has elapsed
Counts up from 0 with internal oscillation
clock as source clock
Operation can be started after oscillation
stabilization time has elapsed
After Reset
XX
/8) has