UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 851

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) CSIEn control register 0 (CEnCTL0)
The CEnCTL0 register controls the operation of CSIEn.
These registers can be read or written in 8-bit or 1-bit units. Writing the CEnTMS, CEnDIR, and CEnSIT bits is
enabled only when CEnTXE bit = 0 and CEnRXE bit = 0.
Reset sets this register to 00H.
Caution Accessing the CEnCTL0 register is prohibited in the following statuses. For details, refer to
CEnCTL0
(n = 0, 1)
3.4.9 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock
After reset: 00H
CHAPTER 18 CLOCKED SERIAL INTERFACE E WITH FIFO (CSIE)
Caution Be sure to clear bits 0 and 1 to “0”. If these bits are set to 1,
CEnPWR
CEnPWR
• The CSIEn unit is reset when the CEnPWR bit = 0, and CSIEn is stopped. To
• When rewriting the CEnPWR bit from 0 to 1 or from 1 to 0, simultaneously
• The CEnTXE bit is reset when the CEnPWR bit is cleared to 0.
• When the CEnPWR bit = 1, after the CEnTXE bit has been cleared to 0, setting
CEnTXE
operate CSIEn, first set the CEnPWR bit to 1.
rewriting the bits other than the CEnCTL0.CEnPWR register is prohibited.
When the CEnPWR bit = 0, rewriting the bits other than the CEnPWR bit of the
CEnCTL0 register, and the CEnTX0, CEnTX0L, and CEnSTR registers is
prohibited.
the CEnTXE bit to 1 before 2 cycles of the operation clock (f
The transmit operation is enabled after the CEnTXE bit has been set to 1, and 2
cycles of the operation clock (f
< >
0
1
0
1
CSIEn operation disables
CSIEn operation enables
Disables transmission operation.
Enables transmission operation.
R/W
CEnTXE CEnRXE CEnTMS
the operation is not guaranteed.
< >
Address: CE0CTL0 FFFFFB00H, CE1CTL0 FFFFFB40H
User’s Manual U19601EJ2V0UD
< >
Disables CSIEn operation/Specifies inhibited
Enables or disables transmission
XX
) have elapsed.
< >
CEnSIT
< >
CEnSIT
XX
) elapse is disabled.
0
0
(1/2)
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