UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 511

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from
the TOT01 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and
restarted. (The output of the TOT00 pin is inverted. The TOT01 pin outputs a high level regardless of the status
(high/low) when a trigger occurs.)
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal (INTTT0CC1) is generated when the count value of the 16-bit counter matches the
value of the CCR1 buffer register.
counter matches the value of the CCRn buffer register and the 16-bit counter is cleared to 0000H.
used as the trigger (n = 0, 1).
16-bit timer/event counter T waits for a trigger when the TT0CE bit is set to 1. When the trigger is generated, the
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The compare match request signal (INTTT0CC0) is generated the next time the 16-bit counter counts after its
The value set to the TT0CCRn register is transferred to the CCRn buffer register when the count value of the 16-bit
The valid edge of an external trigger input (TENC00), or setting the software trigger (TT0CTL1.TT0EST bit) to 1 is
External trigger input
(TENC00 pin input)
INTTT0CC0 signal
INTTT0CC1 signal
TT0CCR0 register
TT0CCR1 register
TOT00 pin output
TOT01 pin output
Active level width = (Set value of TT0CCR1 register) × Count clock cycle
Cycle = (Set value of TT0CCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TT0CCR1 register)/(Set value of TT0CCR0 register + 1)
16-bit counter
TT0CE bit
FFFFH
0000H
Figure 9-22. Basic Timing in External Trigger Pulse Output Mode
trigger
Wait
for
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Active level
width (D
Cycle (D
D
1
1
)
D
0
User’s Manual U19601EJ2V0UD
0
+ 1)
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
D
D
0
1
D
1
D
0
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
509