UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 771

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.7.3 Continuous transmission operation
• In single mode (UBnFIC0.UBnMOD bit = 0)
• If pending mode is specified (UBnFIC0.UBnITM bit = 0) in FIFO mode
• If pointer mode is specified (UBnFIC0.UBnITM bit = 1) in FIFO mode
In the single mode, the next data can be written to the UBnTX register as soon as the transmit shift register
has started a shift operation. The timing of transfer can be identified by the transmission enable interrupt
request signal (INTUBnTIT). By writing the next transmit data to the UBnTX register via the INTUBnTIT signal
within one data frame transmission period, data can be transmitted without an interval and an efficient
communication rate can be realized.
Caution Confirm that the UBnSTR.UBnTSF bit is 0 before executing initialization during transmission
If transmit data of at least the number set as the transmit trigger by UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0
bits and 16 bytes or less is written to transmit FIFO, transmission starts.
If the pending mode is specified in the FIFO mode, as many of the next transmit data as the number set as the
trigger by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits can be written to transmit FIFO as soon as the
transmit shift register has started shifting the last data of the specified number of data. The timing of transfer
can be identified by the INTUBnTIT signal. By writing as many of the next transmit data as the number set as
the trigger to transmit FIFO or writing the data to the FIFO within the transmission period of the data in transmit
FIFO via the INTUBnTIT signal, data can be transmitted without an interval and an efficient communication
rate can be realized.
Caution Confirm that the UBnSTR.UBnTSF bit is 0 before executing initialization during transmission
If the pointer mode is specified in the FIFO mode, a INTUBnTIT signal occurs and the next data can be written
to transmit FIFO as soon as the transmit shift register has started shifting the number of transmit data set as
the trigger. At this time, as many data as the number of empty bytes of transmit FIFO can be written by
referencing the UBnFIS1 register. The timing of transfer can be identified by the INTUBnTIT signal. By writing
as many of the next transmit data as the number specified as the trigger to transmit FIFO or writing the data to
the FIFO within the transmission period of the data in transmit FIFO via the INTUBnTIT signal, data can be
transmitted without an interval and an efficient communication rate can be realized.
Caution Confirm that the UBnSTR.UBnTSF bit is 0 before executing initialization during transmission
Remark
processing. If initialization is executed while the UBnTSF bit is 1, the transmit data is not
guaranteed.
processing (this can also be done by the FIFO transmission end interrupt request signal
(INTUBnTIF)). If initialization is executed while the UBnTSF bit is 1, the transmit data is not
guaranteed. To write transmit data to transmit FIFO by DMA, set the number of transmit data
specified as the trigger by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits to 1 byte; otherwise
the operation will not be guaranteed.
processing (this can also be done by the FIFO transmission end interrupt request signal
(INTUBnTIF)). If initialization is executed while the UBnTSF bit is 1, the transmit data is not
guaranteed.
n = 0, 1
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
User’s Manual U19601EJ2V0UD
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