UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1051

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.3.7 Baud rate control function
(1) Prescaler
(2) Data bit time (8 to 25 time quanta)
Time segment 1 (TSEG1)
Time segment 2 (TSEG2)
reSynchronization Jump Width
(SJW)
Remark IPT: Information Processing Time
The CAN controller has a prescaler that divides the clock (f
CAN protocol layer base clock (f
21.6 (12) CAN0 module bit rate prescaler register (C0BRP)).
One data bit time is defined as shown in Figure 21-18.
The CAN controller sets the data bit time by replacing it with the bit timing parameters such as time segment 1,
time segment 2, and reSynchronization Jump Width (SJW), as shown in Figure 21-18. Time segment 1 is
equivalent to the total of the propagation (prop) segment and phase segment 1 that are defined by the CAN
protocol specification. Time segment 2 is equivalent to phase segment 2.
1 Time Quanta = 1/f
Segment name
TQ: Time Quanta
Sync segment
TQ
2TQ to 16TQ
1TQ to 8TQ
1TQ to 4TQ
Settable range
TQ
Prop segment
Figure 21-18. Segment Setting
) that is the CAN module system clock (f
CHAPTER 21 CAN CONTROLLER
User’s Manual U19601EJ2V0UD
Time segment 1 (TSEG1)
Data bit time (DBT)
IPT of the CAN controller is 0TQ. To conform to the CAN
protocol specification, therefore, a length equal or less to
phase segment 1 must be set here. This means that the
length of time segment 1 minus 1TQ is the settable upper
limit of time segment 2.
The length of time segment 1 minus 1TQ or 4TQ,
whichever smaller.
Phase segment 1
Notes on setting to conform to CAN specification
CAN
Sample point (SPT)
) supplied to CAN. This prescaler generates a
Phase segment 2
Time segment 2
CANMOD
(TSEG2)
−
) divided by 1 to 256 (see
1049