UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 378

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

376
(c) Notes on rewriting TABnCCR0 register
To change the value of the TABnCCR0 register to a smaller value, stop counting once and then change the
set value.
If the value of the TABnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter
may overflow.
Remarks 1. Interval time (1):
If the value of the TABnCCR0 register is changed from D
less than D
has been rewritten. Consequently, the value of the 16-bit counter that is compared is D
Because the count value has already exceeded D
overflows, and then counts up again from 0000H. When the count value matches D
signal is generated and the output of the TOABn0 pin is inverted.
Therefore, the INTTABnCC0 signal may not be generated at the interval time “(D
or “(D
+ 1) × Count clock period”.
INTTABnCC0 signal
TABnCCR0 register
TOABn0 pin output
2
+ 1) × Count clock cycle” originally expected, but may be generated at an interval of “(10000H + D
2. n = 0, 1
16-bit counter
1
TABnOL0 bit
, the count value is transferred to the CCR0 buffer register as soon as the TABnCCR0 register
TABnCE bit
Interval time (NG): (10000H + D
Interval time (2):
FFFFH
0000H
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
L
Interval time (1)
(D
(D
User’s Manual U19601EJ2V0UD
1
2
+ 1) × Count clock cycle
+ 1) × Count clock cycle
D
1
D
1
2
+ 1) × Count clock cycle
D
2
2
Interval time (NG)
, however, the 16-bit counter counts up to FFFFH,
D
1
1
to D
2
while the count value is greater than D
D
2
D
2
Interval
time (2)
D
2
1
+ 1) × Count clock cycle”
2
2
, the INTTABnCC0
.
2
but
2