UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 757

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
UBnRT3
•
•
•
Set the number of receive FIFO receive data to be the trigger.
Each time data of the specified number has been stored from the receive shift
register to receive FIFO, the INTUBnTIR interrupt is generated.
In the pending mode (UBnFIC0.UBnIRM bit = 0), the INTUBnTIR signal is
generated under the conditions of the pending mode.
In the pointer mode (UBnFIC0.UBnIRM bit = 1), the number of receive data set as
the trigger can be only 1 byte (UBnRT3 to UBnRT0 bits = 0000), and other settings
are prohibited. If a setting of other than 1 byte is made, the operation is not
guaranteed.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
UBnRT2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
UBnRT1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
UBnRT0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
User’s Manual U19601EJ2V0UD
transmit FIFO set as trigger
1 byte
2 bytes
3 bytes
4 bytes
5 bytes
6 bytes
7 bytes
8 bytes
9 bytes
10 bytes
11 bytes
12 bytes
13 bytes
14 bytes
15 bytes
16 bytes
Number of data of
Pointer mode Pending mode
Settable
Setting
prohibited
Settable
(2/2)
755