UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 828

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.6.7 UART reception
bit to 1. In the reception wait status, the RXDCn pin is monitored and start bit detection is performed.
recognized if the RXDCn pin is low level at the start bit sampling point. After a start bit has been recognized, the
receive operation starts, and serial data is saved to the UARTCn receive shift register according to the set baud rate.
of the UARTCn receive shift register is written to the UCnRX register. However, if an overrun error (UCnSTR.UCnOVE
bit) occurs, the receive data at this time is not written to the UCnRX register and is discarded.
reception continues until the reception position of the first stop bit, and INTUCnR is output following reception
completion.
826
The reception wait status is set by setting the UCnCTL0.UCnPWR bit to 1 and then setting the UCnCTL0.UCnRXE
Start bit detection is performed using a two-step detection routine.
First the rising edge of the RXDCn pin is detected and sampling is started at the falling edge. The start bit is
When the reception completion interrupt request signal (INTUCnR) is output upon reception of the stop bit, the data
Even if a parity error (UCnSTR.UCnPE bit) or a framing error (UCnSTR.UCnFE bit) occurs during reception,
Remark
RXDCn
INTUCnR
UCnRX
n = 0 to 5 (V850ES/JH3-E)
n = 0 to 7 (V850ES/JJ3-E)
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
Start
bit
D0
Figure 17-18. UART Reception
D1
User’s Manual U19601EJ2V0UD
D2
D3
D4
D5
D6
D7
Parity
bit
Stop
bit