UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1483

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.5.2 Transmit function
stored in the transmit FIFO by the DMAC in the Ethernet controller via DMA transfer, and outputs that transmit frame
to a PHY device. If a collision is detected, the frame is retransmitted by using a random back-off algorithm. The status
information of each transmit frame, such as excessive transmit delays and collisions exceeding the maximum number,
is reflected in the TXSTATUS register, and the number of times each event has occurred in all transmit frames is
counted by statistics counters.
The Ethernet controller generates a transmit frame as defined by IEEE802.3 from the transmit packet data that is
(1) Transmit frame
(2) Transmission clock
(3) Carrier sense signal (CRS)
(4) Collision detection (COL) and retransmission
The transmit frame defined by IEEE802.3 consists of the following six fields (refer to Figure 23-3 Basic Frame
Structure).
• Preamble
• Frame start delimiter (SFD)
• Destination address (DA)
• Source address (SA)
• Length field (LEN)
• Data and frame check sequence (FCS)
For transmission, the Ethernet controller generates the preamble, frame start delimiter, and FCS data.
The Ethernet controller operates in synchronization with the transmission clock (TXCLK) supplied by an
external PHY device. Transmit packet data stored in the transmit FIFO by DMA transfer is synchronized in the
FIFO with TXCLK and output to the PHY device. IEEE802.3 defines the frequency of TXCLK as 25 MHz±100
ppm when the data rate is 100 Mbps and 2.5 MHz±100 ppm when the data rate is 10 Mbps.
During half-duplex communication, if a carrier is detected (CRS = 1) after the Ethernet controller has stored
transmit data in the FIFO, and transmission is enabled, the Ethernet controller postpones transmission until the
end of the carrier (CRS = 0). After the carrier ends, transmission is started when the inter-packet gap (IPG)
count set by the IPGT register has been reached.
If no carrier is detected (CRS = 0) when transmission is enabled and if the IPG count is reached after the
carrier immediately before has ended, transmission is started immediately.
When a frame is transmitted from the source terminal, the carrier sense signal is looped back from the PHY
device and transmitted (received). If the carrier sense signal is masked during transmission from the source
terminal by the system (PHY) configured by the user, the Ethernet controller detects a carrier sense error but
this does not affect the transmission itself.
If the Ethernet controller detects a collision during half-duplex communication, it transmits jam data (an error
CRC) and stops transmission.
If fewer than the maximum number of collisions (default value: 15) are detected in the collision window,
transmission is kept waiting by a random back-off algorithm and data in the transmit FIFO is retransmitted (in
this case, data is not captured into the FIFO again by DMA).
If more than exceeding the maximum number of collisions are detected or if a late collision (collision detected
outside the collision window) occurs, transmission is aborted and the transmit data is discarded.
CHAPTER 23 ETHERNET CONTROLLER
User’s Manual U19601EJ2V0UD
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