UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 479
UPD70F3786GJ-GAE-AX
Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3786GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Company:
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
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(14) Noise elimination control register (TTNFC)
Digital noise elimination can be selected for the TIT00, TIT01, TENC00, TENC01, and TECR0 pins. The noise
elimination settings are performed using the TTNFC register.
When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among
f
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution Time equal to the sampling clock × 3 clocks is required until the digital noise eliminator is
XX
, f
XX
/4, f
TTNFC
After reset: 00H
XX
initialized after the sampling clock has been changed. If the valid edge of the TIT00, TIT01,
TENC00, TENC01, and TECR0 pins is input after the sampling clock has been changed and
before the time of the sampling clock × 3 clocks passes, therefore, an interrupt request
signal may be generated. Therefore, when using the external trigger function, the external
event function, the capture trigger function, and the encoder function of TMT, enable TMT
operation after the sampling clock × 3 clocks have elapsed.
/8, f
XX
TTNFEN
/16, f
TTNFEN
TTNFC2
Remarks 1. Since sampling is performed three times, the noise width for reliably
< >
0
1
0
0
0
0
1
1
XX
Other than above
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
/32, and f
Digital noise elimination not executed
Digital noise elimination executed
TTNFC1
R/W
2. In the case of noise with a width smaller than 2 sampling clocks, an
0
0
0
1
1
0
0
eliminating noise is 2 sampling clocks.
interrupt request signal is generated if noise synchronized with the
sampling clock is input.
XX
Address: FFFFF726H
/64. Sampling is performed 3 times.
TTNFC0
User’s Manual U19601EJ2V0UD
0
1
0
1
0
1
0
Settings of digital noise elimination
f
f
f
f
f
f
Setting prohibited
XX
XX
XX
XX
XX
XX
/4
/8
/16
/32
/64
0
0
Digital sampling clock
TTNFC2 TTNFC1 TTNFC0
477
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