UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1082

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1080
(3) CAN0 global automatic block transmission control register (C0GMABT)
(a) Read
(b) Write
(a) Read
The C0GMABT register is used to control the automatic block transmission (ABT) operation.
Caution Before changing the normal operation mode with ABT to the initialization mode, be sure
Remarks 1. Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0.
Cautions 1. Do not set the ABTTRG bit to 1 in the initialization mode. If the ABTTRG bit is set to 1
After reset: 0000H
C0GMABT
C0GMABT
ABTTRG
ABTCLR
0
1
0
1
to set the C0GMABT register to the default value (0000H). After setting, confirm that the
C0GMABT register is initialized to 0000H.
2. When the automatic block transmission engine is cleared by setting the ABTCLR bit to 1, the
2. Do not set the ABTTRG bit to 1 while the C0CTRL.TSTAT bit is set to 1. Directly
Clearing the automatic transmission engine is completed.
The automatic transmission engine is being cleared.
Automatic block transmission is stopped.
Automatic block transmission is under execution.
The operation is not guaranteed if the ABTCLR bit is set to 1 while the ABTTRG bit is set to
1.
ABTCLR bit is automatically cleared to 0 as soon as the requested clearing processing is
complete.
in the initialization mode, the operation is not guaranteed after the CAN module has
entered the normal operation mode with ABT.
confirm that the TSTAT bit = 0 before setting the ABTTRG bit to 1.
15
15
0
7
0
0
7
0
R/W
Address: 03FEC006H
14
14
0
6
0
0
6
0
CHAPTER 21 CAN CONTROLLER
Automatic block transmission engine clear status bit
User’s Manual U19601EJ2V0UD
Automatic block transmission status bit
13
13
0
5
0
0
5
0
12
12
4
0
4
0
0
0
11
11
0
3
0
0
3
0
10
10
0
2
0
0
2
0
ABTCLR
ABTCLR
Set
9
0
1
9
1
0
ABTTRG
ABTTRG
ABTTRG
Clear
Set
8
0
0
8
0
(1/2)