UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1691

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
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34.1.3 Maskable functions
functions are listed below.
34.1.4 Register
Reset, NMI, INTWDT2, WAIT, and HLDRQ signals can be masked.
The maskable functions with the debugger (ID850QB) and the corresponding V850ES/JH3-E and V850ES/JJ3-E
(1) On-chip debug mode register (OCDM)
The OCDM register is used to select the normal operation mode or on-chip debug mode. This register is a
special register and can be written only in a combination of specific sequences (see 3.4.8 Special registers).
This register is also used to specify whether a pin provided with an on-chip debug function is used as an on-
chip debug pin or as an ordinary port/peripheral function pin. It also is used to disconnect the internal pull-
down resistor of the P54/INTP11/DRST pin.
The OCDM register can be written only while a low level is input to the DRST pin.
This register can be read or written in 8-bit or 1-bit units.
NMI0
NMI2
STOP
HOLD
RESET
WAIT
Maskable Functions with ID850QB
CHAPTER 34 ON-CHIP DEBUG FUNCTION
Table 34-2. Maskable Functions
User’s Manual U19601EJ2V0UD
NMI pin input
Non-maskable interrupt request signal (INTWDT2) generation
HLDRQ pin input
Reset signal generation by RESET pin input, low-voltage
detector, clock monitor, or watchdog timer (WDT2) overflow
WAIT pin input
Corresponding V850ES/JH3-E and V850ES/JJ3-E Functions
1689

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