UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1046

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note
1044
Error active
Error passive
Bus-off
Type
The value of the transmit error counter (TEC) does not carry any meaning if BOFF has been set. If an error
that increments the value of the transmission error counter by 8 while the counter value is in a range of 248 to
255 occurs, the counter is not incremented and the bus-off state is assumed.
Transmission
Reception
Transmission
Reception
Transmission
Reception
Transmission
Operation
0 to 95
0 to 95
96 to 127
96 to 127
128 to 255
128 or more
256 or more
(not indicated)
Value of Error
Counter
Table 21-13. Types of Error States
Note
CHAPTER 21 CAN CONTROLLER
User’s Manual U19601EJ2V0UD
TECS1, TECS0 = 00
TECS1, TECS0 = 01
TECS1, TECS0 = 11
BOFF = 1,
TECS1, TECS0 = 11
RECS1, RECS0 = 00
RECS1, RECS0 = 01
RECS1, RECS0 = 11
Indication of C0INFO
Register
• Outputs an active error flag (6 consecutive dominant-
• Outputs a passive error flag (6 consecutive
• Transmits 8 recessive-level bits, in between
• Communication is not possible.
• If the initialization mode is set, after request to transit
level bits) on detection of the error.
recessive-level bits) on detection of the error.
transmissions, following an intermission (suspend
transmission).
However, when the frame is received, no messages
are stored and the following operations are
performed.
<1> TSOUT toggles.
<2> REC is incremented/decremented.
<3> VALID bit is set.
to an operation mode other than the initialization
mode, 11 consecutive recessive-level bits are
generated 128 times, and then the error counter is
reset to 0 and the error active state can be restored.
Operation Specific to Error State