UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 970

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

968
(7) IIC division clock select registers 0 to 2 (OCKS0 to OCKS2)
(8) IIC shift registers n (IICn)
The OCKSm registers control the I
These registers control the I
the OCKS1 register, and the I
These registers can be read or written in 8-bit units.
Reset sets these registers to 00H.
The IICn registers are used for serial transmission/reception (shift operations) synchronized with the serial
clock. These registers can be read or written in 8-bit units, but data should not be written to the IICn registers
during a data transfer.
Access (read/write) the IICn registers only during the wait period. Accessing these registers in communication
states other than the wait period is prohibited. However, for the master device, the IICn registers can be
written once only after the transmission trigger bit (IICCn.STTn bit) has been set to 1.
A wait state is released by writing the IICn registers during the wait period, and data transfer is started.
Reset sets these registers to 00H.
After reset: 00H
(m = 0 to 2)
IICn
OCKSm
After reset: 00H
Remark
Remark
OCKSTHm
OCKSENm
7
0
0
0
0
1
0
1
0
R/W
R/W
Stops I
Enables I
OCKSm1
n = 0 to 3 (V850ES/JH3-E)
n = 0 to 4 (V850ES/JJ3-E)
n = 0 to 4 (V850ES/JJ3-E)
n = 0 to 3 (V850ES/JH3-E)
2
C00 division clock via the OCKS0 register, the I
0
0
0
1
1
0
6
2
C03 and I
2
Cn division clock operation
Address: OCKS0 FFFFF340H, OCKS1 FFFFF344H, OCKS2 FFFFF348H
2
Cn division clock operation
2
OCKSm0
C0n division clock.
0
1
0
1
0
0
User’s Manual U19601EJ2V0UD
2
5
Address: IIC0 FFFFFD80H, IIC1 FFFFFD90H, IIC2 FFFFFDA0H,
CHAPTER 20 I
C04 division clocks via the OCKS2 register.
Operation setting of I
OCKSENm OCKSTHm
f
f
f
f
f
XX
XX
XX
XX
XX
/4
/6
/8
/10
/2
IIC3 FFFFFDB0H, IIC4 FFFFFBC0H
4
Selection of I
2
C BUS
2
Cn division clock
3
2
Cn division clock
0
OCKSm1 OCKSm0
2
2
C01 and I
1
2
C02 division clocks via
0