UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 572

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

570
Clearing Method
Figure 9-53. Operation Example (When TT0SCE Bit = 0, TT0ECS1 and TT0ECS0 Bits = 01, and TT0UDS1 and
Encoder clear input
(TENC00 pin input)
(TENC01 pin input)
(6) Function to clear counter to 0000H by encoder clear signal (TECR0 pin)
Table 9-9. Relationship Between TT0SCE Bit and TT0ZCL, TT0BCL, TT0ACL, TT0ECS1, and TT0ECS0 Bits
(TECR0 pin input)
TT0CNT register
Peripheral clock
The 16-bit counter can be cleared to 0000H by the input signal of the TECR0 pin in two ways which are
selected by the TT0IOC3.TT0SCE bit.
TT0IOC3.TT0ZCL, TT0IOC3.TT0BCL, TT0IOC3.TT0ACL, TT0IOC3.TT0ESC1, and TT0IOC3.TT0ECS0 bits.
The counter can be cleared by the methods described below only in the encoder compare mode.
(a) Clearing method <1>: By detecting edge of encoder clear signal (TECR0 pin) (TT0SCE bit = 0)
<1>
<2>
Encoder input
Encoder input
timing signal
INTTT0EC
When the TT0SCE bit = 0, the 16-bit counter is cleared to 0000H in synchronization with the peripheral
clock if the valid edge of the TECR0 pin specified by the TT0ECS1 and TT0ECS0 bits is detected. At this
time, an encoder clear interrupt request signal (INTTT0EC) is generated. When the TT0SCE bit = 0, the
settings of the TT0ZCL, TT0BCL, and TT0ACL bits is invalid.
interrupt
Count
TT0SCE Bit
0
1
N
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
TT0ZCL Bit
Invalid
Valid
N + 1
User’s Manual U19601EJ2V0UD
Counter clear
TT0UDS0 Bits = 11)
The TT0SCE bit also controls, depending on its setting, the
0000H
TT0BCL Bit
Invalid
Valid
0001H
TT0ACL Bit
Invalid
Valid
TT0ECS1, TT0ECS0 Bits
0002H
Invalid
Valid