UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1125

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.9.5 Multi buffer receive block function
sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message
buffer type. These message buffers can be allocated in any area in the message buffer memory, and they are not
necessarily to be allocated adjacent to each other.
the same ID is set to each message buffer. If the first message whose ID matches an ID of the message buffers is
received, it is stored in message buffer 10. At this point, the DN bit of message buffer 10 is set, prohibiting overwriting
the message buffer.
a message with a matching ID is received, it is sequentially (in the ascending order) stored in message buffers 12, 13,
and so on. Even when a data block consisting of multiple messages is received, the messages can be stored and
received without overwriting the previously received matching-ID data.
message buffer. For example, if a data block consists of k messages, k message buffers are initialized for reception
of the data block. The IE bit in message buffers 0 to (k-2) is cleared to 0 (interrupts disabled), and the IE bit in
message buffer k-1 is set to 1 (interrupts enabled). In this case, a reception completion interrupt occurs when a
message has been received and stored in message buffer k-1, indicating that MBRB has become full. Alternatively,
by clearing the IE bit of message buffers 0 to (k-3) and setting the IE bit of message buffer k-2, a warning that MBRB
is about to overflow can be issued.
of storing data in a single message buffer.
The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers
Suppose, for example, the same message buffer type is set to 10 message buffers, message buffers 10 to 19, and
When the next message with a matching ID is received, it is received and stored in message buffer 11. Each time
Whether a data block has been received and stored can be checked by setting the C0MCTRLm.IE bit of each
The basic conditions of storing receive data in each message buffer for the MBRB are the same as the conditions
Cautions 1. MBRB can be configured for each of the same message buffer types. Therefore, even if a
Remark m = 00 to 31
2. MBRB does not have a ring buffer structure. Therefore, after a message is stored in the
3. MBRB operates based on the reception and storage conditions; there are no settings
4. With MBRB, “matching ID” means “matching ID after mask”. Even if the ID set to each
5. Priority among each MBRB conforms to the priority shown in 21.9.1 Message reception.
message buffer of another MBRB whose ID matches but whose message buffer type is
different has a vacancy, the received message is not stored in that message buffer, but
instead discarded.
message buffer having the highest number in the MBRB configuration, a newly received
message will no longer be stored in the message buffer in the order from the lowest message
buffer number.
dedicated to MBRB, such as function enable bits. By setting the same message buffer type
and ID to two or more message buffers, MBRB is automatically configured.
message buffer is not the same, if the ID that is masked by the mask register matches, it is
considered a matching ID and the buffer that has this ID is treated as the storage destination
of a message.
CHAPTER 21 CAN CONTROLLER
User’s Manual U19601EJ2V0UD
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