UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1047

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Receiving node detects an error (except bit error in the active error
flag or overload flag).
Receiving node detects dominant level following error flag of error
frame.
Transmitting node transmits an error flag.
[As exceptions, the error counter does not change in the following
cases.]
<1> ACK error is detected in error passive state and dominant level
<2> A stuff error is detected in an arbitration field that transmitted a
Bit error detection while active error flag or overload flag is being
output (error-active transmitting node)
Bit error detection while active error flag or overload flag is being
output (error-active receiving node)
When the node detects 14 consecutive dominant-level bits from the
beginning of the active error flag or overload flag, and then
subsequently detects 8 consecutive dominant-level bits.
When the node detects 8 consecutive dominant levels after a
passive error flag
When the transmitting node has completed transmission without
error (±0 if error counter = 0)
When the receiving node has completed reception without error
is not detected while the passive error flag is being output.
recessive level as a stuff bit, but a dominant level is detected.
(b) Error counter
(c) Occurrence of bit error in intermission
The error counter counts up when an error has occurred, and counts down upon successful transmission
and reception. The error counter counts up immediately after error detection.
An overload frame is generated.
Caution If an error occurs, it is controlled according to the contents of the transmission error
counter and reception error counter before the error occurred. The value of the error
counter is incremented after the error flag has been output.
State
CHAPTER 21 CAN CONTROLLER
Table 21-14. Error Counter
User’s Manual U19601EJ2V0UD
No change
No change
+8
+8
No change
+8 (transmitting)
–1
No change
Transmission Error Counter
(TEC7 to TEC0 Bits)
+1 (REPS bit = 0)
+8 (REPS bit = 0)
No change
No change
+8 (REPS bit = 0)
+8 (receiving, REPS bit = 0)
No change
• –1 (1 ≤ REC6 to REC0 ≤
• ±0 (REC6 to REC0 = 0,
• Any value of 119 to 127
Reception Error Counter
127, REPS bit = 0)
REPS bit = 0)
is set (REPS bit = 1)
(REC6 to REC0 Bits)
1045