UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1526

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.6.5 Error occurrence
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(1) Error write back
(2) Error interrupt
If a bus error occurs when the data buffer is accessed during transmission or reception, an error interrupt is
generated and DMA is stopped. In addition, the U and D bits of the first descriptor of the packet are set to 1
(the U bit may have already been set to 1 in some cases). The U, D, and E bits of the descriptor in which the
error occurred are set also to 1.
If an overflow occurs during reception, the U and O bits of the first descriptor of a packet are set (the U bit may
have already been set in some cases). The U and E bits of the descriptor in which the overflow occurred are
also set.
The error interrupt is generated by an access error in the data buffer and also by the occurrence of as
descriptor access error. The occurrence of the error interrupt can be confirmed by the setting of INTMS.RBEI
and INTMS.TBEI.
If a data buffer or descriptor access error occurs, the descriptor chain containing the descriptor in which the
error occurred must be reorganized.
Transmission If a descriptor or data buffer access error occurs, TBEI is set to 1 and DMA is stopped.
Reception
Transmission is not restarted until TXS is next set to 1.
If a descriptor or data buffer access error occurs, RBEI is set and DMA is stopped.
Reception is not performed until RXS is next set.
transferred from the FIFO is discarded.
If packet transfer has not been started, the packet is not discarded. Even if a bus error occurs
as a result of a reception overflow, the processing is the same as that when a descriptor
access error occurs.
CHAPTER 23 ETHERNET CONTROLLER
User’s Manual U19601EJ2V0UD
At the same time, the packet being