UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 715

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.5 Operation
15.5.1 Basic operation
<1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the
<2> When A/D conversion is started, the voltage input to the selected analog input channel is sampled by the
<3> When the sample & hold circuit samples the input channel for a specific time, it enters the hold status, and
<4> Set bit 9 of the successive approximation register (SAR), and set the compare voltage generation DAC to
<5> The voltage difference between the voltage of the compare voltage generation DAC and the analog input
<6> Next, bit 8 of the SAR is automatically set and the next comparison is started. Depending on the value of bit
<7> This comparison is continued to bit 0 of the SAR.
<8> When comparison of the 10 bits is complete, the valid digital result remains in the SAR, and is then
<9> In one-shot select mode, conversion is stopped
ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set,
conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external or
timer trigger mode.
sample & hold circuit.
holds the input analog voltage until A/D conversion is complete.
(1/2) AV
voltage is compared by the voltage comparator. If the analog input voltage is higher than (1/2) AV
MSB of the SAR remains set. If it is lower than (1/2) AV
9, to which a result has been already set, the compare voltage generation DAC is selected as follows.
• Bit 9 = 1: (3/4) AV
• Bit 9 = 0: (1/4) AV
This compare voltage and the analog input voltage are compared and, depending on the result, bit 8 is
manipulated as follows.
Analog input voltage ≥ Compare voltage: Bit 8 = 1
Analog input voltage ≤ Compare voltage: Bit 8 = 0
transferred to and stored in the ADA0CRn register. After that, an A/D conversion end interrupt request signal
(INTAD) is generated.
scanning once
cleared to 0. In continuous scan mode, repeat steps <2> to <8> for each channel.
Remark
Note In the external trigger mode, timer trigger mode 0, or timer trigger mode 1, the trigger standby status
is entered.
REF0
The trigger standby status means the status after the stabilization time has elapsed.
.
Note
. In continuous select mode, repeat steps <2> to <8> until the ADA0M0.ADA0CE bit is
REF0
REF0
CHAPTER 15 A/D CONVERTER
User’s Manual U19601EJ2V0UD
Note
. In one-shot scan mode, conversion is stopped after
REF0
, the MSB is reset.
REF0
, the
713