UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 426

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

detected, the count value of the 16-bit counter is stored in the TABnCCRm register, and a capture interrupt request
signal (INTTABnCCm) is generated.
generates an overflow interrupt request signal (INTTABnOV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TABnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the
CLR instruction by software.
424
When the TABnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIABnm pin is
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
Remark
Note The V850ES/JH3-E only includes the TIAB13 pin; it is not provided with the TIAB03 pin. When
INTTABnCC3 signal
TABnCCR3 register
m = 0 to 3,
n = 0, 1
INTTABnCC0 signal
INTTABnCC1 signal
INTTABnCC2 signal
TABnCCR0 register
TABnCCR1 register
TABnCCR2 register
TIABn3 pin input
INTTABnOV signal
TIABn0 pin input
TIABn1 pin input
TIABn2 pin input
using the V850ES/JH3-E, the TAB0CCR3 register and the INTTAB0CCR3 signal cannot be used.
Figure 8-30. Basic Timing in Free-Running Timer Mode (Capture Function)
16-bit counter
TABnOVF bit
TABnCE bit
FFFFH
0000H
Note
Note
Note
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
0000
0000
0000
0000
D
20
D
00
D
User’s Manual U19601EJ2V0UD
30
D
10
CLR instruction
D
Cleared to 0 by
00
D
D
20
D
01
D
10
30
D
11
D
21
D
31
D
01
CLR instruction
Cleared to 0 by
D
11
D
12
D
D
21
D
02
31
D
22
D
32
D
D
Cleared to 0 by
CLR instruction
02
12
D
03
D
D
D
13
32
22
D
D
33
03
D
23
D
13
D
D
33
23