UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1457

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
24 to 16
11 to 0
(12) RXFINF2: Reception status 2 register
Bit
Access
Address
Default value 0000 0800H. This register is cleared to its default value by all types of resets.
Caution Be sure to set bits 31 to 25 and 15 to 12 to “0”.
RREMAIN7 RREMAIN6 RREMAIN5 RREMAIN4 RREMAIN3 RREMAIN2 RREMAIN1 RREMAIN0
RPCNT[8:0]
RREMAIN
[11:0]
RPCNT7
31
23
15
Name
R
R
R
R
0
0
7
This register is read-only, in 32-bit units.
002E 0248H
RPCNT6
These bits indicate the number of packets (start flag to end flag) in the receive FIFO.
The value of this field is incremented when one packet has been written by the MAC (a packet that
has not been received but discarded does not cause the value of this field to increment).
The value of this field is decremented when a packet has been read from the DMAC in the
Ethernet controller or, if the packet is canceled, when the internal operation to cancel the packet
(discard the packet) has been completed.
These bits indicates the remaining receive FIFO capacity (in bytes).
Bits 1 and 0 are ignored and always indicate 0, 0, because the size of the receive FIFO is 32 bits
(4 bytes).
30
22
14
R
R
R
R
0
0
6
RPCNT5
CHAPTER 23 ETHERNET CONTROLLER
29
21
13
R
R
R
R
0
0
5
User’s Manual U19601EJ2V0UD
RPCNT4
28
20
12
R
R
R
R
0
0
4
RREMAIN11 RREMAIN10 RREMAIN9 RREMAIN8
RPCNT3
27
19
11
R
R
R
R
0
3
Description
RPCNT2
26
18
10
R
R
R
R
0
2
RPCNT1
25
17
R
R
R
R
0
9
1
RPCNT8
RPCNT0
24
16
R
R
R
R
8
0
1455

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