UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1634

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
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Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
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28.3.2 Reset operation by watchdog timer 2
(WDT2RES signal generation), a system reset is executed and the hardware is initialized to the initial status.
and the reset status is then automatically released.
1632
Main clock oscillator (f
Subclock oscillator (f
Internal oscillator (f
Peripheral clock (f
Internal system clock (f
CPU clock (f
CPU
Watch dog timer 2
Internal RAM
I/O lines (ports/alternate-function pins)
On-chip peripheral I/O register
On-chip peripheral functions other than
above
When watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow
Following watchdog timer 2 overflow, the reset status is entered and lasts the predetermined time (analog delay),
The main clock oscillator is stopped during the reset period.
CPU
)
Item
XX
R
)
to f
XT
Table 28-2. Hardware Status During Watchdog Timer 2 Reset Operation
X
)
)
XX
XX
),
/1,024)
Oscillation stops
Oscillation continues
Oscillation stops
Operation stops
Operation stops
Initialized
Operation stops (initialized to 0)
Undefined if power-on reset or CPU access and reset input conflict (data is damaged).
Otherwise value immediately after reset input is retained.
High impedance
Initialized to specified status, OCDM register retains its value.
Operation stops
CHAPTER 28 RESET FUNCTIONS
User’s Manual U19601EJ2V0UD
During Reset
Oscillation starts
Oscillation starts
Operation starts after securing oscillation
stabilization time
Operation starts after securing oscillation
stabilization time (initialized to f
Program execution after securing
oscillation stabilization time
Counts up from 0 with internal oscillation
clock as source clock.
Operation can be started after securing
oscillation stabilization time.
After Reset
XX
/8)

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